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ISL22326
Dual Digitally Controlled Potentiometers (XDCPTM)
Data Sheet July 17, 2006 FN6176.0
Low Noise, Low Power, I2C(R) Bus, 128 Taps
The ISL22326 integrates two digitally controlled potentiometers (XDCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the two DCP's IVR to the corresponding WRs. The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* Two potentiometers in one package * 128 resistor taps * I2C serial interface - Three address pins, up to eight devices/bus * Non-volatile storage of wiper position * Wiper resistance: 70 typical @ 3.3V * Shutdown mode * Shutdown current 5A max * Power supply: 2.7V to 5.5V * 50k or 10k total resistance * High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T <55C * 14 Ld TSSOP * Pb-free plus anneal product (RoHS compliant)
Pinout
ISL22326 (14 LD TSSOP) TOP VIEW
VCC SHDN RH0 RL0 RW0 A2 SCL 1 2 3 4 5 6 7 14 13 12 11 10 9 8 A1 A0 RH1 RL1 RW1 GND SDA
Ordering Information
PART NUMBER ISL22326UFV14Z (Notes 1, 2) ISL22326WFV14Z (Notes 1, 2) NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "-TK" suffix for 1,000 Tape and Reel option PART MARKING 22326 UFVZ 22326 WFVZ RESISTANCE OPTION (k) 50 10 TEMP. RANGE (C) -40 to +125 -40 to +125 PACKAGE 14 Ld TSSOP (Pb-free) 14 Ld TSSOP (Pb-free) PKG. DWG. # M14.173 M14.173
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL22326 Block Diagram
VCC
SCL SDA A0 A1 A2 I2C INTERFACE POWER-UP INTERFACE, CONTROL AND STATUS LOGIC
RH1
WR1
RW1 RL1
RH0 NONVOLATILE REGISTERS
WR0
RW0 RL0
SHDN
GND
Pin Descriptions
TSSOP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL VCC SHDN RH0 RL0 RW0 A2 SCL SDA GND RW1 RL1 RH1 A0 A1 Power supply pin Shutdown active low input "High" terminal of DCP0 "Low" terminal of DCP0 "Wiper" terminal of DCP0 Device address input for the I2C interface Open drain I2C interface clock input Open drain Serial data I/O for the I2C interface Device ground pin "Wiper" terminal of DCP1 "Low" terminal of DCP1 "High" terminal of DCP1 Device address input for the I2C interface Device address input for the I2C interface DESCRIPTION
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Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to VCC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125C ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
Thermal Information
Thermal Resistance (Typical, Note 3) 14 Lead TSSOP package . . . . . . . . . . . . . . . . . . . .
JA (C/W)
100
Recommended Operating Conditions
Temperature Range (Extended Industrial). . . . . . . .-40C to +125C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW Wiper Current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -0.8V for all pins.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W option U option MIN TYP (NOTE 5) 10 50 -20 50 80 70 0 10/10/25 Voltage at pin from GND to VCC 0.1 1 200 VCC +20 MAX UNIT k k % ppm/C (Note 19) ppm/C (Note 19) V pF A
PARAMETER RH to RL Resistance
RH to RL Resistance Tolerance End-to-End Temperature Coefficient
W and U option W option U option
RW VRH, VRL CH/CL/CW (Note 19) ILkgDCP
Wiper Resistance VRH and VRL Terminal Voltages Potentiometer Capacitance Leakage on DCP Pins
VCC = 3.3V @ +25C, wiper current = VCC/RTOTAL VRH and VRL to GND
VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0 or 1) INL (Note 10) DNL (Note 9) ZSerror (Note 7) FSerror (Note 8) VMATCH (Note 11) TCV (Note 12) Integral Non-linearity Differential Non-linearity Zero-scale Error Monotonic over all tap positions Monotonic over all tap positions W option U option Full-scale Error W option U option DCP to DCP Matching Any two DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals DCP register set to 40 hex -1 -0.5 0 0 -5 -2 -2 1 0.5 -1 -1 1 0.5 5 2 0 0 2 LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) ppm/C
Ratiometric Temperature Coefficient
4
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Analog Specifications
SYMBOL Over recommended operating conditions unless otherwise stated. (Continued) TEST CONDITIONS MIN TYP (NOTE 5) MAX UNIT
PARAMETER
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0 or 1) RINL (Note 16) RDNL (Note 15) Roffset (Note 14) Integral Non-linearity Differential Non-linearity Offset DCP register set between 10h and 7Fh; monotonic over all tap positions DCP register set between 10h and 7Fh; monotonic over all tap positions W option U option RMATCH (Note 17) DCP to DCP Matching Any two DCPs at the same tap position with the same terminal voltages -1 -0.5 0 0 -2 1 0.5 1 0.5 5 2 2 MI (Note 13) MI (Note 13) MI (Note 13) MI (Note 13) MI (Note 13)
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 ICC2 ISB PARAMETER VCC Supply Current (volatile write/read) VCC Supply Current (non-volatile write/read) VCC Current (standby) TEST CONDITIONS fSCL read and write states) = 400kHz; SDA = Open; (for I2C, active, MIN TYP (NOTE 5) MAX 0.5 3 5 7 3 5 3 5 2 4 -1 1.5 1.5 1.5 2.0 0.2 VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state 3 2.6 1 UNIT mA mA A A A A A A A A A s s s V V/ms ms
fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) VCC = +5.5V @ +85C, I2C interface in standby state VCC = +5.5V @ +125C, I2C interface in standby state VCC = +3.6V @ +85C, I2C interface in standby state VCC = +3.6V @ +125C, I2C interface in standby state
ISD
VCC Current (shutdown)
VCC = +5.5V @ +85C, I2C interface in standby state VCC = +5.5V @ +125C, I2C interface in standby state VCC = +3.6V @ +85C, I2C interface in standby state VCC = +3.6V @ +125C, I2C interface in standby state
ILkgDig tWRT (Note 18) tShdnRec (Note 18)
Leakage Current, at Pins A0, A1, A2, SHDN, SDA, and SCL DCP Wiper Response Time DCP Recall Time from Shutdown Mode
Voltage at pin from GND to VCC SCL falling edge of last bit of DCP data byte to wiper new position From rising edge of SHDN signal to wiper stored position and RH connection SCL falling edge of last bit of ACR data byte to wiper stored position and RH connection
Vpor VccRamp tD
Power-on Recall Voltage VCC Ramp Rate Power-up Delay
Minimum VCC at which memory recall occurs
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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP (NOTE 5) MAX UNIT
EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 20) Non-volatile Write Cycle Time Temperature T <55C 1,000,000 50 12 20 Cycles Years ms
SERIAL INTERFACE SPECS VIL VIH Hysteresis VOL Cpin (Note 19) fSCL tsp tAA tBUF A2, A1, A0, SHDN, SDA, and SCL Input Buffer LOW Voltage A2, A1, A0, SHDN, SDA, and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 4mA A2, A1, A0, SHDN, SDA, and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL falling edge to SDA output data valid Any pulse narrower than the max spec is suppressed SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window 1300 -0.3 0.7*VCC 0.05* VCC 0 0.4 10 400 50 900 0.3*VCC VCC+0.3 V V V V pF kHz ns ns ns
Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time Measured at the 30% of VCC crossing Measured at the 70% of VCC crossing SCL rising edge to SDA falling edge; both crossing 70% of VCC From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC From SDA rising edge to SCL falling edge; both crossing 70% of VCC From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window From 30% to 70% of VCC From 70% to 30% of VCC Total on-chip and off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2~2.5k For Cb = 40pF, max is about 15~20k
tLOW tHIGH tSU:STA tHD:STA tSU:DAT
1300 600 600 600 100
ns ns ns ns ns
tHD:DAT
Input Data Hold Time
0
ns
tSU:STO tHD:STO tDH
STOP Condition Setup Time STOP Condition Hold Time for Read, or Volatile Only Write Output Data Hold Time
600 1300 0
ns ns ns
tR tF Cb Rpu
SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL SDA and SCL Bus Pull-up Resistor Off-chip
20 + 0.1 * Cb 20 + 0.1 * Cb 10 1
250 250 400
ns ns pF k
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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL tSU:A tHD:A NOTES: 5. Typical values are for TA = +25C and 3.3V supply voltage 6. LSB: [V(RW)127 - V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)127 - VCC]/LSB. 9. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 10. INL = [V(RW)i - i * LSB - V(RW)0]/LSB for i = 1 to 127. 11. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 12. TC V = --------------------------------------------------------------------------------------------- x ---------------- for i = 16 to 112 decimal, T = -40C to +125C. Max( ) is the maximum value of the wiper [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 165C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 13. MI = |RW127 - RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 14. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 15. RDNL = (RWi - RWi-1)/MI -1, for i = 16 to 127. 16. RINL = [RWi - (MI * i) - RW0]/MI, for i = 16 to 127. 17. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. [ Max ( Ri ) - Min ( Ri ) ] 10 18. TC R = --------------------------------------------------------------- x ---------------- for i = 16 to 112, T = -40C to +125C. Max( ) is the maximum value of the resistance and Min ( ) is [ Max ( Ri ) + Min ( Ri ) ] 2 165C the minimum value of the resistance over the temperature range. 19. This parameter is not 100% tested. 20. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal nonvolatile write cycle.
6
PARAMETER A2, A1 and A0 Setup Time A2, A1 and A0 Hold Time
TEST CONDITIONS Before START condition After STOP condition
MIN 600 600
TYP (NOTE 5)
MAX
UNIT ns ns
SDA vs SCL Timing
tF tHIGH tLOW tR tsp tHD:STO
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
A0, A1, and A2 Pin Timing
START SCL CLK 1 STOP
SDA tSU:A A0, A1, OR A2 tHD:A
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[
Typical Performance Curves
VCC
100 90
WIPER RESISITANCE ()
Vcc = 3.3V, T = 125C
1.4
80 70 60 50 40 30 20 10 0 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
1.2 T =125 C 1
VCC
Isb (A)
0.8
0.6
Vcc = 3.3V, T = 20C
Vcc = 3.3V, T = -40C
0.4 T =25 C 0.2
0 2.7 3.2 3.7 4.2 4.7 5.2
Vcc, V
FIGURE 2. STANDBY ICC vs VCC
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W)
0.2 Vcc = 2.7V 0.1
DNL (LSB) INL (LSB)
0.2
T = 25C
T = 25C 0.1 Vcc = 2.7V
0
0
-0.1 Vcc = 5.5V -0.2 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
-0.1 Vcc = 5.5V -0.2 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
1.30 1.10 0.90
ZSerror (LSB)
0.00
10k
-0.30 Vcc = 2.7V
FSerror (LSB)
50k
Vcc = 5.5V
0.70 0.50 0.30 0.10 -0.10 -0.30 -40 -20 0 50k Vcc = 5.5V Vcc = 2.7V
-0.60 -0.90 10k -1.20 -1.50 -40
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. ZSerror vs TEMPERATURE
FIGURE 6. FSerror vs TEMPERATURE
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ISL22326 Typical Performance Curves
0.4 0.2
DNL (LSB) INL (LSB)
(Continued)
0.4
T=25C
0.2 0
T = 25C
0 -0.2 Vcc =2.7V -0.4 -0.6 16 Vcc =5.5V
Vcc = 5.5V -0.2 Vcc = 2.7V -0.4 -0.6
36
56
76
96
116
16
36
56
76
96
116
TAP PO SITIO (DECIMAL) N
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN Rheostat MODE FOR 10k (W)
FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR 10k (W)
END TO END RTOTAL CHANGE (%)
1.00 Vcc = 2.7V 0.50
TCv (ppm/C)
105
50k
90 75 60 45 30 15 0
10k
0.00
-0.50 Vcc = 5.5V -1.00 -40 10k
50k
-20
0
20
40
60
80
100
120
16
36
56
76
96
TEMPERATURE (C)
TAP POSITION (DECIM AL)
FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
INPUT
300 250
TCr (ppm/C)
OUTPUT
200 150 100 50 0 16
10k
50k
Wiper at Mid Point (position 40h) Rtotal = 9.5k
36
56
76
96
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR Rheostat MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (2.6MHz)
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ISL22326 Typical Performance Curves
(Continued)
Wiper Mid Point Movement from 3Fh to 40h
FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h
FIGURE 14. LARGE SIGNAL SETTLING TIME
Pin Descriptions
Potentiometers Pins
RHi and RLi (i = 0, 1) The high (RHi) and low (RLi) terminals of the ISL22326 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. RWi (i = 0,1) RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. SHDN The SHDN pin forces the resistor to end-to-end open circuit condition on RHi and shorts RWi to RLi. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically OR'd with SHDN bit in ACR register. I2C interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation.
Bus Interface Pins
Serial Data Input/Output (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. Serial Clock (SCL) This is the serial clock input of the I2C serial interface. SCL requires an external pull-up resistor, since it is an open drain input. Device Address (A2 - A0) The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL22326. A maximum of 8 ISL22326 devices may occupy the I2C serial bus.
Principles of Operation
The ISL22326 is an integrated circuit incorporating two DCPs with their associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometers and memory. The resistor arrays are comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions.
RH
RW
RL
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
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When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi are recalled and loaded into the corresponding WRi to set the wipers to the initial value. The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described below in Table 2. The VOL bit at access control register (ACR[7]) determines whether the access is to wiper registers WRi or initial value registers IVRi.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL SHDN WIP
DCP Description
Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR register of a DCP contains all ones (WR[6:0]= 7Fh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL22326 is being powered up, all WRs are reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, all WRs will be reload with the value stored in corresponding non-volatile Initial Value Registers (IVRs). The WRs can be read or written to directly using the I2C serial interface as described in the following sections. The I2C interface Address Byte has to be set to 00h or 01h to access the WR of DCP0 or DCP1 respectively.
0
0
0
0
0
If VOL bit is 0, the non-volatile IVRi registers are accessible. If VOL bit is 1, only the volatile WRi are accessible. Note, value is written to IVRi register also is written to the corresponding WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically OR'd with SHDN pin. When this bit is 0, DCP is in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR[5]) is read only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the IVRi, WRi or ACR while WIP bit is 1.
I2C Serial Interface
The ISL22326 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL22326 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 16). On power-up of the ISL22326 the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22326 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 16). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 16). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode.
Memory Description
The ISL22326 contains seven non-volatile and three volatile 8-bit registers. Memory map of ISL22326 is on Table 1. The two non-volatile registers (IVRi) at address 0 and 1, contain initial wiper value and volatile registers (WRi) contain current wiper position. In addition, five non-volatile General Purpose registers from address 2 to address 6 are available.
TABLE 1. MEMORY MAP ADDRESS 8 7 6 5 4 3 2 1 0 General Purpose General Purpose General Purpose General Purpose General Purpose IVR1 IVR0 NON-VOLATILE -- Reserved Not Available Not Available Not Available Not Available Not Available WR1 WR0 VOLATILE ACR
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An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 17). The ISL22326 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22326 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 1010 as the four MSBs, and the following three bits matching the logic values present at pins A2, A1, and A0. The LSB is the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation (See Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
Logic values at pins A2, A1, and A0 respectively
1 (MSB)
0
1
0
A2
A1
A0
R/W (LSB)
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE SLAVE
1 0 1 0 A2 A1 A0 0 A C K
0000 A C K A C K
FIGURE 18. BYTE WRITE SEQUENCE
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FN6176.0 July 17, 2006
ISL22326
S T A R T S T A IDENTIFICATION R BYTE WITH T R/W=1
SIGNALS FROM THE MASTER
IDENTIFICATION BYTE WITH R/W=0
ADDRESS BYTE
A C K
A C K
S AT CO KP
SIGNAL AT SDA
1 0 1 0 A2 A1 A0 0 A C K
0000 A C K
1 0 1 0 A2 A1 A0 1 A C K
SIGNALS FROM THE SLAVE
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 19. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22326 responds with an ACK. At this time, the device enters its standby state (See Figure 18). Device can receive more than one byte of data by auto incrementing the address after each received byte. Note after reaching the address 08h, the internal pointer "rolls over" to address 00h. The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next non-volatile write. Thus, non-volatile registers must be written individually.
Read Operation
A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 19). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL22326 responds with an ACK. Then the ISL22326 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a ACK and a STOP condition) following the last bit of the last Data Byte (See Figure 19). The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 08h, the pointer "rolls over" to 00h, and the device continues to output data for each ACK received. In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again.
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FN6176.0 July 17, 2006
ISL22326 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN6176.0 July 17, 2006

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